Verilog Strengths

Definition

The strength declaration construct is used for modeling net type variables for a close correspondence with physical wires.

Syntax

(Strength1, Strength0)

(Strength0, Strength1)

Strength1: (specifies the strength when the net is driven with value “1”)
              supply1,  strong1,  pull1,  large1,  weak1,  medium1,  small1,  highz1

Strength0: (specifies the strength when the net is driven with value “0”)
               supply0,  strong0,  pull0,  large0,  weak0,  medium0,  small0,  highz0

Description

Strengths can be used to resolve which value should appear on a net or gate output. There are two types of strengths:                   

drive strength (See Example 1) and charge strength (See Example 2).

    The drive strengths can be used for nets (except trireg net), gates, and UDPs.

         The charge strengths can be used only for trireg nets.

    The drive strength types are supply, strong, pull, weak, and highz strengths.

         The charge strength types are large, medium and small strengths.

All strengths can be ordered by their value. The supply strength is the strongest and the highz strength is the weakest strength level. Strength value can be displayed by system tasks ($display, $monitor - by using of the %v characters).

Strength	Value	Value displayed by display tasks
Supply	7	Su
Strong	6	St
Pull	5	Pu
Large	4	La
Weak	3	We
medium	2	Me
Small	1	Sm
Highz	0	HiZ

                    Table:  Strengths ordered by decreasing value

There are different scenarios of driving strength and is mentioned below –

    If two or more drivers drive a signal then it will have the value of the strongest driver (See Example 3).

    If two drivers of a net have the same strength and value, then the net result will have the same value and strength (See Example 4).

    If two drivers of a net have the same strength but different values then signal value will be unknown and it will have the same strength as both drivers (See Example 5).

    If one of the drivers of a net has an H or L value, then signal value will be n1n2X, where n1 is the strength value of the driver that has the smaller strength, and n2 is strength value of driver that has the larger strength (See Example 6).

** The combinations (highz0, highz1) and (highz1, highz0) are illegal.

SAMPLE CODE1:

and (strong1, weak0) and1(out, in1, in2);

Instance of and gate with  strong1 strength and weak0 strength specified.

SAMPLE CODE2:

trireg (medium) t;

The charge strength declaration for  trireg  net.

SAMPLE CODE3:

buf (strong1, weak0)  buff1 (y, a);

buf (pull1, supply0)  buff2 (y, b);

If a = 0 and b = 0 then y will be 0 with supply strength because both gates will set y to 0 and supply (7) strength has bigger value than weak (3) strength.

If a = 0 and b = 1 then y will be 1 with pull strength because buff1 will set y to 0 with weak (3) strength and buff2 will set y to 1 with pull (5) strength (pull strength is stronger than the weak strength).

If a = 1 and b = 0 then y will be 0 with supply strength because buff1 will set y to 1 with strong (6) strength and buff2 will set y to 0 with supply (7) strength (supply strength is stronger than the strong strength).

If a = 1 and b = 1 then y will be 1 with strong strength because buff1 will set y to 1 with strong (6) strength and buff2 will set y to 1 with pull (5) strength.

SAMPLE CODE4:

buf (strong1, weak0) buf1 (y, a);

buf (strong1, weak0) buf2 (y, b);

 If a = 0 and b = 0 then y will be 0 with weak strength.

If a = 1 and b = 1 then y will be 1 with strong strength.

SAMPLE CODE5:

buf (strong1, weak0) buf1 (y, a);

buf (weak1, strong0) buf2 (y, b);

If a = 1 and b = 0 then y will be x with strong strength.

SAMPLE CODE6:

bufif0 (strong1, weak0) buf1 (y, i1, ctrl);

bufif0 (strong1, weak0) buf2 (y, i2, ctrl);

If ctrl = x, i1 = 0, and i2 = 1 then y will be x with 36X strength, because buf1 will set y to L with strong strength (StL - 6) and buf2 will set y to H with weak strength (WeH - 3).

Important Notes

If one of the drivers has an H or L value, then the output value will be X.

Write a verilog code to swap contents of two registers with and without a temporary register?

With temp register (using blocking assignment)

always @ (posedge clock)
   begin
     temp = b;
     b = a;
     a = temp;
   end
 
Without temp register (using non-blocking assignment)

always @ (posedge clock)
   begin
     a <= b;
     b <= a;
   end

What is the difference between blocking and non-blocking assignments ?

In Verilog , we have two forms of the procedural assignment statement:

      1. blocking assignment (represented by "=" operator)
      2. non-blocking assignment (represented by "<=" operator).

In blocking assignment statement (i.e. "=" operator), whole statement executes in Active region of current time stamp and then control goes to the next statement.

Whereas,

In non-blocking assignment statement (i.e. "<=" operator), right-hand sides gets evaluated first in Active region and assigns it to left-hand side in the NBA region of the current time stamp.

------------------------------------------------------------------------------------------------------------
Example code is mentioned below
------------------------------------------------------------------------------------------------------------
module blocking;
reg [0:7] A, B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;

$display("Blocking: A= %b B= %b", A, B );
A = 3;
#1 A <= A + 1; // non-blocking procedural assignment
B <= A + 1;
#1 $display("Non-blocking: A= %b B= %b", A, B );
end
endmodule

-----------------------------------------------------------------------------------------------------------------------------------------         OUTPUT        ---------------------------------------------------------
------------------------------------------------------------------------------------------------------------
Blocking:         A= 00000100     B= 00000101
Non-blocking: A= 00000100     B= 00000100


The non-blocking assignments use the old values of the variables at the beginning of the current time unit and to assign the registers new values at the end of the current time unit. It shows how register transfers occur in hardware systems.
Blocking procedural assignment is used for combinational logic, whereas non-blocking procedural assignment for sequential.

How to generate clock in Verilog ?

 There are many ways to generate clock in Verilog. Some of them are listed below:

Method #1 Using always block and negation operator for 50% duty cycle
initial begin
clk = 0;
end
always
 begin
#5 clk = ~clk;
  end

Method #2 Using always block, negation operator and parameter for 50% duty cycle
 parameter simulation_cycle = 10;
initial begin
clk = 0;
end
always begin
#(simulation_cycle/2) clk = ~clk;
end
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
Method #3 Using forever block and  negation operator for 50% duty cycle
initial begin
clk = 0;
forever begin
#5 clk = ~clk;
end
end

Method #4 Using forever block, negation operator and parameter for 50% duty cycle
    parameter simulation_cycle = 10;
initial begin
clk = 0;
forever begin
#(simulation_cycle/2) clk = ~clk;
end
end

//------------------------------------------------------------------------------------//
//------------------------------------------------------------------------------------//
Method #5 using always block, directed low time and high time value for 50% duty cycle
initial begin
clk = 0;
end
always begin
#5 clk = 0;
#5 clk = 1;
end

Method #6 using always block, directed low time and high time value and parameter for 50% duty cycle
    parameter simulation_cycle = 10;
initial begin
clk = 0;
end
always begin
#(simulation_cycle/2) clk = 0;
#(simulation_cycle/2) clk = 1;
end

 There are different other ways also to generate the clock, but commonly these methods are used.

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