What is the difference between blocking and non-blocking assignments ?

In Verilog , we have two forms of the procedural assignment statement:

      1. blocking assignment (represented by "=" operator)
      2. non-blocking assignment (represented by "<=" operator).

In blocking assignment statement (i.e. "=" operator), whole statement executes in Active region of current time stamp and then control goes to the next statement.

Whereas,

In non-blocking assignment statement (i.e. "<=" operator), right-hand sides gets evaluated first in Active region and assigns it to left-hand side in the NBA region of the current time stamp.

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Example code is mentioned below
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module blocking;
reg [0:7] A, B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;

$display("Blocking: A= %b B= %b", A, B );
A = 3;
#1 A <= A + 1; // non-blocking procedural assignment
B <= A + 1;
#1 $display("Non-blocking: A= %b B= %b", A, B );
end
endmodule

-----------------------------------------------------------------------------------------------------------------------------------------         OUTPUT        ---------------------------------------------------------
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Blocking:         A= 00000100     B= 00000101
Non-blocking: A= 00000100     B= 00000100


The non-blocking assignments use the old values of the variables at the beginning of the current time unit and to assign the registers new values at the end of the current time unit. It shows how register transfers occur in hardware systems.
Blocking procedural assignment is used for combinational logic, whereas non-blocking procedural assignment for sequential.