How to generate clock in Verilog ?

 There are many ways to generate clock in Verilog. Some of them are listed below:

Method #1 Using always block and negation operator for 50% duty cycle
initial begin
clk = 0;
end
always
 begin
#5 clk = ~clk;
  end

Method #2 Using always block, negation operator and parameter for 50% duty cycle
 parameter simulation_cycle = 10;
initial begin
clk = 0;
end
always begin
#(simulation_cycle/2) clk = ~clk;
end
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Method #3 Using forever block and  negation operator for 50% duty cycle
initial begin
clk = 0;
forever begin
#5 clk = ~clk;
end
end

Method #4 Using forever block, negation operator and parameter for 50% duty cycle
    parameter simulation_cycle = 10;
initial begin
clk = 0;
forever begin
#(simulation_cycle/2) clk = ~clk;
end
end

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Method #5 using always block, directed low time and high time value for 50% duty cycle
initial begin
clk = 0;
end
always begin
#5 clk = 0;
#5 clk = 1;
end

Method #6 using always block, directed low time and high time value and parameter for 50% duty cycle
    parameter simulation_cycle = 10;
initial begin
clk = 0;
end
always begin
#(simulation_cycle/2) clk = 0;
#(simulation_cycle/2) clk = 1;
end

 There are different other ways also to generate the clock, but commonly these methods are used.

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