With temp register (using blocking assignment)
always @ (posedge clock)
begin
temp = b;
b = a;
a = temp;
end
Without temp register (using non-blocking assignment)
always @ (posedge clock)
begin
a <= b;
b <= a;
end
always @ (posedge clock)
begin
temp = b;
b = a;
a = temp;
end
Without temp register (using non-blocking assignment)
always @ (posedge clock)
begin
a <= b;
b <= a;
end
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ReplyDeleteRajeev, you can refer the internal phasing
ReplyDeletehttp://www.microelectronicslab.com/KnowBase/Verilog-IQ.html#Q2
a and b will be as input or wire ...i hv been trying but give complet code plz
ReplyDeleteHi,
DeleteWe have uploaded the complete code. please try it out.
enjoy and keep learning ,keep sharing :-)
Regards,
Rajeev
where is the complete code
Delete
ReplyDeletemodule swap(input[1:0]a,b,
input clk);
reg[1:0]tempa,tempb,temp; //reg tempb;
always @ (posedge clk)
begin
tempa = a;
tempb = b;
temp=tempa;
tempa = tempb;
tempb = temp ;
end
endmodule
module swap(clk);
ReplyDeleteinput clk;
integer a,b,temp;
initial
begin
a = 10; b = 20;
end
always@(posedge clk)
begin
#50temp=b;
#50b=a;
#50a=temp;
end
endmodule
how to write testbench to it
DeleteTq
ReplyDeleteModule register(D,clk,RST,Q);
ReplyDeleteInput D;
Input clk;
Input RST;
Output reg Q;
Always@(posedge clk)
If(!RST)
Q<=0;
Else
Q<=D;
Else
Q=1;
Endmodule
8bit number from dip switch and swap the nibble and display on led
ReplyDeletevery nice
ReplyDelete